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To mitigate near-zero line sensitivity, a two-transistor (2-T) voltage reference is biased using a current source, thereby offsetting the drain-induced barrier-lowering (DIBL) effect intrinsic to the 2-T core, consequently enhancing line sensitivity performance. This compensation circuit, operating within a supply voltage range of 6 to 18 volts, generates a 3.078-volt reference voltage with a Monte Carlo simulated line sensitivity of 0.035%/volt, all while consuming onl
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